1. Field of Invention
The present invention relates semiconductor memories and in particular flash memories using dual bit flash memory cells.
2. Description of Related Art
Bit line decoding is a common component to all types of DRAM, SRAM and flash memory arrays. Smaller chip area means lower cost; and therefore, as many memory cells are packed into a small space as possible. However, the sensing circuitry, which determines the value of the memory cell, may require significant area. This is one of the reasons that a single sensing circuit is usually shared between many memory cells in order to reduce cost. The function of a bit line decoder is to select the correct bit line and connect it to a corresponding sense amplifier.
FIG. 1 shows a conventional bit line decoder connected to a NOR-type floating gate flash memory array. It should be noted that for the NOR-type array, each memory cell column has a unique bit line, and the source diffusions of the memory cells are connected horizontally through the array.
FIG. 2 shows a higher density dual-bit type array, in which the source lines are combined with the bit lines and run vertically. U.S. Pat. No. 6,011,725 (Eitan) and patent application Ser. No. 09/426,692 filed Oct. 25, 1999 describe different types of dual-bit memory arrays. The basic commonality between them is that a single word line and one bit line is shared between two hard-bits (left and right of each word gate). For a single hard-bit operation, two bit lines are needed to be selected at the same time. One will provide the source voltage and the other will provide the drain voltage, depending on whether the left or right hand bit is selected. Thus, it can be seen that the bit line decoder for a dual bit array needs to be more complex than the NOR-type decoder.
In U.S. Pat. No. 6,011,725 (Eitan), a single hard bit storage site is selected for operations. Care and consideration is taken to ensure that the unselected hard bit storage site sharing the same bit line does not experience undue disturb effects. In patent application Ser. No. 10/099,030 filed Mar. 15, 2002, a new memory cell selection is introduced. Instead of selecting two bit lines for one hard-bit, three bit lines are selected for two hard bits. By selecting the two hard bit storage sites simultaneously, disturb effects can be reduced. Also bit line decode is greatly simplified because hard bits are selected as pairs and there is no longer a need to differentiate between the left and right bits.
In patent application Ser. No. 09/810,122 filed Mar. 19, 2001 another type of dual bit flash memory cell array with a metal bit line is described, shown in FIG. 3. Although the cell area is slightly larger, the process is simpler than the diffusion bit line array. Instead of having a diffusion bit line, a single diffusion to a metal contact is shared between four hard bits, which lowers the bit line resistance. Control gates run parallel to the word line, and bit lines run orthogonal to both the control lines and the word lines. Bit line selection depends on both the y column address as well as an odd or even designation of the CG line
It is an objective of the present invention is to provide a bit line decoder scheme that selects one memory cell containing two storage sites in an array of dual bit memory cells.
It is another objective of the present invention to use the bit line decoder scheme with both the diffusion bit line MONOS and the metal bit line MONOS arrays.
It is still another objective of the present invention to provide a bit line decoder circuit, which incorporates the voltage selection requirements for a dual bit memory array.
It is yet another objective of the present invention to selectively connect bit lines to a voltage source through decoding transistors.
It is further an objective of the present invention to selectively connect two bit lines to two intermediate data lines and selectively connect the intermediate data lines to sense amplifiers through decoding transistors.
It is still further an objective of the present invention to reduce the number of signals produced by the decoder logic by incorporating the voltage selection requirements for the dual bit memory array by a third intermediate data line.
In the present invention a bit line decoder scheme is described in which one memory cell containing two storage sites is selected from an array of flash memory cells each containing two storage sites. In a first embodiment a first decoding unit comprises transistors that connect bit lines to a voltage source. The bit lines function both as source lines and as drain lines to the memory cells. A second decoding unit comprises transistors that selectively connect the bit lines of the flash memory array to intermediate data lines. A third decoder unit comprises transistors that connect the intermediate data lines to the memory sense amplifiers. This allows a memory storage site to be connected to each of two sense amplifiers simultaneously while a bias voltage is selectively applied the bit lines of the memory array.
In the second embodiment reduces by one the number of decoding units in comparison to the first embodiment. A first decoding unit comprises transistors that selectively connect the bit lines of a flash memory array containing cells with two storage sites to intermediate data lines. The intermediated data lines are connected to sense amplifiers by a second decoding unit. The second decoding unit is also used to connect a voltage to a third intermediate data line in which the voltage is selectively connected to the bit lines through the first decoding unit.